This PDF file contains the front matter associated with SPIE Proceedings Volume 13423, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

As the chip size continues to decrease, the feature size of transistor is getting closer to the optical diffraction limit. When performing the lithography process, the optical proximity effect exists due to the mismatch between the exposure wavelength and the critical dimension of the mask pattern, making it difficult to obtain results on the wafer that are consistent with target pattern. To alleviate this effect, we propose an Optical Proximity Correction (OPC) method with an improved Encoder-Decoder structure. By embedding a coordinate information convolution module, the limitations of the convolution module in dealing with spatial location information are broken through. Moreover, a residual connection is introduced between encoder and decoder, which allows the algorithm to further improve the model's ability to deal with complex layout data by learning the residuals between the inputs and the outputs. The results show that compared with other deep learning algorithms, the proposed method obtains ideal correction results while speeding up the computation.

Accurately and efficiently calculating the near field of the EUV mask with large-scale and complex patterns is a critical part of EUV aerial image simulation. Therefore, a calculation method based on the full-vector beam propagation method is proposed, which successfully realizes ultra-fast near-filed calculation with comparable accuracy for the investigated examples. The proposed method shows strong competitiveness for EUV mask near-field calculation and can also be applied to calculate the EUV aerial image accurately and efficiently by supplementing the projection lens model and vector imaging method.

In this paper, we introduce a cost function driven GAOPC (Genetic Algorithm based Optical Proximity Correction) method for automatic OPC job tuning. Instead of manual review and judgement, the customized cost function is defined in advance to regulate GA convergence direction. Meanwhile, a real time Convergence Check Module is introduced to monitor the running status of GAOPC job. A real product case’s evaluation result shows GAOPC has better performance than baseline with 38% less RMS (worst EP value) and around 82% cycle time reduction. Combined with Convergence Check Module, 31% more cycle time can be saved further.

The source mask-optimization (SMO) is an inevitable computational lithography technique in the fabrication of advance integrate circuit (IC). Meanwhile, the aerial image (AI) blur is an important parameter to approximate the imaging degrade effect of resist and wafer stage during the SMO calculation. In this work, we propose a novel method to evaluate the imaging degrading of the AI blur. The AI blur convolution kernel is first transferred to the frequential space with the Fourier transformation. Then, the frequential coverage of the kernel is compared with the imaging pupil. Larger frequential coverage of the kernel indicates that the AI blur has trivial impact on the imaging, while low frequential coverage revel that the AI blur can degrade the imaging seriously. The proposed method can determine an appropriate range of AI blur setting, which is valuable at the beginning of the SMO process.

As technology nodes shrink and layout sizes grow, layout pattern matching in lithography defect detection becomes increasingly time-consuming. To address this, we propose a fast layout pattern matching algorithm based on spatial indexing. The method first uses geometric information to locate potential matching regions, then employs spatial indexing to divide the layout into sub-regions, quickly excluding irrelevant areas and improving efficiency. Multithreading and compiler optimizations further enhance speed. Experiments show that our approach achieves a 20- 30x speedup over commercial tools while maintaining 100% accuracy, demonstrating its effectiveness for very large-scale integrated circuit defect detection.

In IC manufacturing, there is a great demand for CD-SEM image production in the areas of computational lithography, hotspot detection, yield improvement, etc. Whereas, directing CD-SEM metrology is time-cost and skillfulness since it requires metrology engineers to manage creating CD-SEM recipes on their experience gauge by gauge, including determining suitable metrology methods, corresponding parameters, optimal Auto Focus and Addressing position based on shapes and circumstances of the metrology target. To address this, this work has proposed an efficient and labor-free way to create CD-SEM recipes via a High-Speed-Steaming (HSS) file in Recipe Director to measure lots of points within minutes automatically. For each metrology position, its numerical geometry feature obtained in Line Scan analysis achieves the ability of measurement type determining and relative parameters returning. Autofocus and Addressing position searching can be well done with sliding window patches and Fourier descriptors in the meanwhile. With an aim to facilitate massive gauge measurements and convenient usage, a Windows-platform software is also developed for engineers.

The critical dimension scanning electron microscope (CDSEM) plays an essential role in measuring sub-nanometer scale patterns after lithography and etching process. However, its measurement capabilities are limited, making it difficult to accurately measure complex pattern such as tip-to-tip or tip to side structures. Additionally, it’s very challenging for CDSEM to perform an accurate multiple-layer multiple-process data measurement and process characterization, such as etch bias and channel length/width uniformity. This paper addresses these challenges by performing SEM contours extraction and data analysis on the gate (GT) and active area (AA) stacking structures of Static Random Access Memory (SRAM) bit cell pattern. Utilizing SIEMENS EDA's Calibre SEMSuite and Calibre OPCVerify tools, we extracted contours from SEM images to analyze process variations at the center, middle, and edge positions of the wafer. By overlaying the contours of ADI and AEI, we determined the etch bias across the entire SRAM bit cell pattern. Additionally, by overlaying the contours of AA and GT, we ascertain the channel width and length (W/L) value of the transistors. This data provides a direction for optimizing SRAM layout design and establishes a systematic method for silicon data analysis.

We introduce an inverse lithography framework where typical grayscale mask tone is penalized toward transparent and opaque transmissions compatible with existing mask writing. Threshold regularization featuring dynamic fine-tuned optimal thresholds for main feature and Sub-Resolution Assist Features (SRAFs) is incorporated into the optimization of lithographic image formation. The optimization flow preludes with the synthesis of a Continuous Transmission Mask (CTM) for the best pattern fidelity; then respective thresholds are applied to main feature and orders of SARF by including the regularization term into the mask synthesis flow where a warp function is devised for binarizing mask transmission with optimal thresholds. Simulations results demonstrate that the proposed approach effectively facilitates the pursuit of comparable lithographic imaging performance while maintaining design flexibility which is essential for both mask design and fabrication.

Process Window Qualification (PWQ) is an essential phase in the semiconductor manufacturing process. The Focus Exposure Matrix (FEM) is the most prevalent technique employed within PWQ. Traditionally, the method relies on spot features, such as Critical Dimensions (CD), and utilizes the Bossung curve for PWQ. However, with intricate circuit layouts and multi-step processes, such as Litho-Etch-Litho-Etch (LELE) sequences, the conventional approach struggles to account for all possible conditions. To address this, we propose an innovative computer vision-based approach for PWQ. Taking the CD as an example, instead of merely measuring the CD of selected patterns, our method scans the entire circuit layout to identify areas prone to defect such as bridge or broken, thereby leading to a more accurate and objective PWQ.

Source-Mask Co-Optimization (SMO) techniques have significantly supported semiconductor manufacturing quality by enhancing imaging contrast and lithographic process control in advanced lithography nodes over the past decade. Through jointly optimizing the design of the illumination source and modifying the reticle patterns on the mask, the SMO technique has provided a viable method to find the best photo process for a given design rule. In SMO, process parameters such as the Exposure Latitude (EL), the Depth of Focus (DoF), the Mask Error Factor (MEF) can be improved through the definition of a cost function. For EUV, there is an added issue that the optical axis is not normal to the reticle. Although the optical axis is normal to the wafer, there still exists shadowing effect and horizontal-vertical linewidth bias (H-V bias) that needs to be considered. Therefore, in our SMO program, we also put the illumination telecentricity at wafer plane into consideration, which may help reduce pattern shift at defocus positions. In this presentation, we provide an example with a minimum pitch of 40 nm, which is commonly used for the 2~3 nm Back-End-Of-the-Line (BEOL) logic technology nodes. In this example, we will discuss the challenges and potential of our SMO technique and we will offer recommendations for EUV SMO implementations in advanced EUV technology nodes. Our analysis indicates that SMO can continue to improve optimal pattern transfer capabilities by simultaneously optimizing both illumination source and mask design.

Edge placement error (EPE) has become a critical metric for ensuring patterning accuracy and optimizing the process window in semiconductor manufacturing. Initially introduced to measure optical proximity correction (OPC) errors, EPE now encompasses a broader set of parameters, including overlay (OV), critical dimension uniformity (CDU), and line width roughness (LWR), making it essential for managing the complexity of advanced multi-patterning processes. Despite its importance, directly measuring EPE remains challenging due to the intricate nature of modern semiconductor devices, often requiring statistical methods for estimation. This paper demonstrates the use of secondary electron (SE) and backscattered electron (BSE) imaging to improve the accuracy and practicality of EPE measurement. By optimizing BSE imaging conditions, layers such as contact and can be visualized simultaneously, allowing for more direct calculations of OV and EPE_interlayer. The optimized imaging conditions also enhance edge definition, improving pattern accuracy and process control. Our results show that SE and BSE imaging offer a more precise method for evaluating EPE and contribute to a better understanding of the factors influencing process window control.

In the OPC development process, the following three problems can delay the entire model process. The first one is that experienced engineers usually need spend a lot of time to filter SEM image for model fitting. The second is that some SEM images CD can’t be measured in first measurement, and it is usually necessary to adjust the measurement recipe for second measurement to obtain the wafer CD value. The third one is that when model fitting is finished, engineers need to align SEM image to simulation contour to verify the model results, it takes a lot of time and has accuracy error. These problems can be solved by the SiV (Silicon Verification) tool.

There are many kinds of OPC test pattern in Contact (CT) layer, and different measurement methods are used to measure the model data, resulting in a large simulation error of y-direction rectangle type patterns in the model. We propose a new method to build OPC model of CT layer by using SEM image contour. In this work, the SEM image contour was extracted by Calibre SEMSuite™, and the measurements of the corresponding test pattern was calculated according to the image contour. The CD-SEM (critical dimension scanning electron microscope) measurement data of anchor point was used to calibrate the modeling data and then the OPC model was built. Compared with the model tuned by CD measurements, the simulation error of y-direction rectangle type patterns caused by measurement method is effectively reduced. Our experiments show that it is feasible to build a high precision OPC model of CT layer by using this method.

Optical proximity correction (OPC) is essential for advanced semiconductor manufacturing beyond 45nm node by improving lithography resolution. However, traditional OPC techniques are limited by scalar imaging models and gradient-based algorithms. This study introduces a physics-driven deep learning OPC scheme that leverages vector imaging model. Guided by inverse lithography technology (ILT), the algorithm requires no extensive datasets, relying instead on varied, randomly generated patterns for training. The results from numerical testing confirm the approach's accuracy and efficiency.

Lithography, one of the key semiconductor manufacturing processes, requires accurate and robust process window analysis to ensure high-yield chip production. Traditional methods often utilize fixed polynomial functions to fit focus-exposure matrix data, which can fail to account for variations across mask patterns and noise in critical dimension measurements, leading to inaccurate evaluation of the process window and best process condition. This paper introduces a stepwise regression approach that iteratively selects statistically significant terms based on p-values. Evaluation through adjusted R2 and window overlapping before and after noise introduction demonstrates the method’s effectiveness in enhancing both accuracy and noise robustness in process window analysis.

Fast Source Optimization (SO) is a critical requirement for the 14-5nm node in integrated lithography online technology. Our previous research introduced Bayesian Compressed Sensing SO (CCS-BCS-SO), which effectively delivered high pattern fidelity. However, its processing speed still lags behind that of compressive sensing (CS) SO. This paper introduces the first application of the iterative shrinkage - thresholding algorithm with RMSProp (RMSProp-ISTA) in compressive sensing. This innovation aims to ensure a high-fidelity pattern while improve convergence speed and accelerating SO. The results indicate that the CCS-RMSProp-ISTA-SO method is three times faster than the CCS-BCS-SO method, achieving the fast SO like CS-SO and the high pattern fidelity of SD-SO.

The increasing complexity and miniaturization of integrated circuits (ICs) have amplified the impact of minor manufacturing defects, which can significantly degrade chip performance and system reliability. Accurate classification of these subtle defects is crucial but challenging due to the intricate features in chip imagery. In this paper, we introduce VSRNet, an enhanced network architecture that leverages the strengths of VGGNet, integrated with Squeeze-and-Excitation (SE) attention mechanisms and residual connections (Res). To further boost classification accuracy, we develop a novel image preprocessing technique that amplifies subtle chromatic aberration, making minor defects more detectable. Experimental evaluations demonstrate that VSRNet consistently outperforms traditional approaches across multiple metrics, with notable improvements observed when incorporating the proposed preprocessing method. This work offers a robust solution for fine-grained defect classification in complex semiconductor manufacturing environments.

During exposure of vector scanning electron beam lithography, the hysteresis effect of scanning coils and the instability of electron beam current will affect the smoothness of the edge of the exposure pattern. To address this issue, this paper proposes a novel scanning strategy, comprising inward spiral scanning along the edges to expose the periphery of the pattern and meandering scanning to achieve uniform exposure inside the pattern. The experimental results demonstrate that the proposed scanning strategy is capable of exposing patterns with smoother edges than the traditional scanning method.

With the continuous resolution shrinking in cutting edge semiconductor industry such as memory device, on product overlay (OPO) control has become more and more challenging. Reticle heating is a critical impact to OPO when DUV light exposes to the reticle, as the thermal expansion of the reticle induces nanos of overlay error on wafer level which directly impacts device function. Reticle heating control functions has been developed to compensate overlay error in current advanced scanners for normal full reticle, of which one layer mask occupies one reticle. However, the heating effect of Multilayer Reticle (MLR), wherein one reticle consists of multiple mask layers, is less discussed. In this paper, we investigated the reticle heating effect to OPO on MLR, and the methods for MLR heating control is proposed.

Optical proximity correction (OPC) plays a critical role in the entire semiconductor manufacturing process. The consistency of identical patterns within the same context becomes increasingly crucial to ensure high performance during OPC processing, especially in areas like SRAM regions. Consistency checking essentially involves the classification of repeated patterns and the comparison of pattern layers (i.e., OPC results) . While SRAM mini-array designs can often be easily identified manually, there are still instances where the OPC team deals with is not mini-array but real designs, which lack sufficient hierarchical information to identify unit cells . Moreover, array designs can vary in type and style. Therefore, a fully automatic and generic method is necessary. This paper presents a fully automatic and generic method for classifying array designs using Calibre Pattern Matching and Calibre equation-based DRC (eqDRC). Unlike the traditional approach of sampling anchors with a fixed pitch and then running pattern classification, this new method first analyzes the array design to identify the actual array region, calculate the array cell size and generate cell markers. With the help of eqDRC, the cell size can be calculated both horizontally and vertically. Sampling anchors followed by identifying the actual cell helps classify repeating structures more effectively. After classification, a report on cell occurrence is generated, allowing only high-occurrence cells to be retained as unit cells. These cells can then be stored in a Pattern Matching Database (PMDB), which also includes OPC layers. Consistency of OPC results can be easily verified by outputting XOR results between the design and the patterns in the PMDB, utilizing the Calibre Partial Matching technique. Reviewing unmatched regions and XOR results helps identify new array types or inconsistent OPC results . This method would be very helpful for OPC engineer to collect the new array cell pattern s and the XOR results can help engineer to identify the process weak points, and if necessary, OPC modifications can be made before tape -out. This approach will significantly shorten the tape-out cycle time.

Line edge roughness (LER) played more critical- role with the semiconductor manufacturing keep shrinking down to new technology nodes. From our previous study, the larger exposure area gives positive impact to LER performance, as more photons can be captured by photoresist, reducing the randomness of photoacid distribution and make line edge smoother. In this paper, we further investigate the litho process impact factors for LER, including Normalized Image Log-Slope (NILS) and exposure energy. Simulation model was setup on top of experiment data, and further expand to different critical dimension (CD) and pitch conditions.

Researchers occasionally use a single photomask to create a stacked structure with identical patterns. This method is cost-effective but also challenging for precise overlay control, due to the lack of coupled overlay marks between successive layers. In this paper, an innovative approach has been developed to address this problem. By shifting the exposure field with a specific offset, the outer overlay mark of the previous layer and the inner overlay mark of the current layer are aligned to the same coordinate position, allowing for accurate measurement of the overlay error. The raw overlay measurement values are then modeled using polynomials and compensated during subsequent runs. The effectiveness of this method has been demonstrated with experiment wafers, and PFA (Physical Failure Analysis) result further confirmed its feasibility for achieving precise overlay in such applications.

Photolithography is a pivotal stage in integrated circuit chip manufacturing, exerting a direct influence on both the performance and yield of the chips. Its efficacy hinges heavily on the meticulous control of parameters such as focus and exposure dose. Traditionally, the production speed is limited by multiply rounds of lengthy production-adjust process. Speeding up this process in manufacturing has become a pressing problem. To tackle this challenge, we introduce a novel framework that integrates a conditional adversarial network (GAN) with a parameter encoding module to predict the SEM images from layout images coupled with photolithography parameters. During the training phase, we first pre-train the model using paired data from layout images to SEM images, then we fine-tune the model with paired image data and corresponding lithography parameters. This proposed adversarial training process ensures that the generated photolithography images are remarkably similar to authentic SEM images. Moreover, the innovative parameter encoding structure allows the GAN to tailor image generation according to specific lithography parameters. Extensive experiments validate the effectiveness of our method, indicating that we have constructed a precise virtual photolithography model capable of predicting SEM images based on layout and parameter inputs. This approach not only effectively forecasts lithography outcomes but also provides essential technical support to address design challenges in the photolithography process, significantly streamlining the path from design to production.

Measurement is a critical aspect of advanced lithography, particularly for evaluating process capabilities in sub-10 nm technology nodes. Traditional manual measurement methods for Scanning Electron Microscopy (SEM) images lack robustness and are inadequate for large-scale analysis, especially for complex 2D features such as dislocations in hexagonal array patterns. To address these limitations, a contour-based algorithm has been developed for measuring Critical Dimension (CD), pitch, and dislocations in hexagonal arrays. By generating virtual layout based on measured CD and pitch, the algorithm enables detailed analysis of placement errors and provides insights into pattern regularity and symmetry. This approach has been verified on SEM images of hexagonal arrays with a pitch of approximately 30 nm, demonstrating its effectiveness in supporting advanced manufacturing process evaluation.

Process miniaturization is a commonly used method in semiconductor manufacturing to achieve higher device density and better device performance at a lower cost. However, with the continuous improvement of process nodes, traditional pattern transfer methods face dual challenges of accuracy and cost. How to achieve accurate pattern transfer is a problem that the industry is facing and urgently needs to solve. This article proposes an innovative process window analysis (PWA) method for optimizing multiple patterning technology (DPT) to improve the success rate of pattern transfer and chip performance. By introducing process window analysis into the layout splitting process, this paper addresses the limitations of traditional judgment based on geometric proximity. This article takes the common odd circle topological graph in double patterning technology as an example, and demonstrates that through OPC (Optical Proximity Correction) optimization and simulated printing, the process window differences between different polygon pairs can be identified. By combining polygons with larger process windows into one group (mask) and splitting polygon pairs with smaller process windows into two masks. This can effectively split the layout and meet the requirements of printability. This method not only avoids the need for redesigning the circuit, but also achieves a design solution that can be immediately put into mass production. The experimental results demonstrate that the method proposed in this paper is an effective solution for layout splitting in DPT mode, providing a new technological approach for the semiconductor manufacturing field.

A non-approximate integral theorem of Fresnel diffraction by rectangle aperture is proposed. The phase term in the Fresnel diffraction integral is retained exactly, the Fresnel obliquity factor is determined by triangle relation, not approximated by paraxial. It’s applied to DUV wavelength similar size of rectangle aperture. The numerical evaluation of diffraction integral provides intensity distribution. The contour profile and fitting rectangle is determined, the alternative phase shift and pattern correction is introduced. The simulation and resolution enhancement of the near field Fresnel diffraction by rectangle aperture, provides a perspective solution of DUV proximity lithography.

Curvilinear mask has better lithography imaging fidelity than rectilinear mask. However, the mask data volume has limited its practical application. Curvilinear Optical Proximity Correction (OPC) outputs much smaller curvilinear mask file sizes than conventional Inverse Lithography Technology (ILT). The current Curvilinear OPC process is computationally intensive. This paper proposes a Curvilinear OPC method adopting quasi-uniform B-spline curves to improve the optimization efficiency. The ask Control Points (MCP) are set by equidistant contour sampling method. Then MCPs are connected by a closed quasi-uniform B-spline curve to characterize the curvilinear mask structure. Besides, the curvilinear mask structure is optimized by Particle Swarm Optimization (PSO) algorithm. Simulations and comparisons verify the superior optimization efficiency of the proposed methods.

Source and mask optimization (SMO) is a crucial resolution enhancement technique for 28nm technology node and beyond in lithography. The allocation method of micromirror array (MMA) is the key to produce the freeform illumination source. The generated illumination source is affected by the computation speed and accuracy of the allocation method. In this paper, an allocation method of micromirror array for deep ultraviolet illumination system is proposed. The computation speed of the proposed method is faster than the traditional method. The experimental results show that the computation efficiency of the proposed method has been improved by at least 50%.

The current SMO method has been employed to improve lithography performance at a point in the Field of View (FOV) without considering the influence of aberrations varies with the relative motion between the wafer and the FOV during exposure (dynamic aberration). Otherwise, the non-uniformity of the image quality in the vertical scanning direction is also ignored which cannot meet the performance at full exposure field. A Source and Mask Optimization (SMO) method is proposed via a dynamic aberration imaging model to compensate for that influence. According to the characteristics of the Deep Ultraviolet Lithography (DUVL) pulse laser, the model performs a weighted summation of the area images at different positions along the scanning path. The cost function is designed to have a weighted sum of representative scanning paths to balance the FOV imaging quality. Compared to the current SMO method, the proposed method effectively reduces pattern error (PAE) and improves average imaging performance across the full field.

Statistical Process Control (SPC) plays a critical role in semiconductor manufacturing, ensuring product quality and yield by monitoring key performance indicators (KPIs) of processes and equipment. As semiconductor nodes continue to shrink, the challenges of process control increases, often requiring the combination of traditional KPIs or the creation of new ones to identify root causes effectively. However, existing SPC systems - both commercially available and those developed in-house - may lack the necessary flexibility and functionality to manage complex data volumes. In our study, we propose a flexible and efficient KPI monitoring system based on KLA visual flow editor software applied specifically to photolithography process control and addresses these critical aspects: Scanner Performance Stability: Monitoring the stability of scanners used in photolithography processes is essential for consistent results. Any deviations can impact product quality and yield. Overlay Fingerprint Changes: Overlay refers to the alignment accuracy of multiple layers during semiconductor manufacturing. Detecting changes in overlay fingerprints helps maintain precise alignment, which is crucial for successful chip fabrication. Metrology Health: Metrology tools measure critical dimensions and other parameters during the manufacturing process. Ensuring the health and accuracy of these tools is vital for reliable data. Our proposed monitoring system leverages powerful data processing capabilities, allowing for customized KPI monitoring tailored to specific user needs. By reducing engineering time and costs, it enhances efficiency in high-volume manufacturing environments.

Over the past decade, the semiconductor industry has rapid development, fueled by Moore's Law. Concurrently, semiconductor manufacturing has consistently progressed, one of the prominent manifestations is the continuous reduction in pattern sizes and pitches. To accommodate these smaller pattern sizes, innovative techniques for enhancing lithography resolution have emerged, like off-axis illumination, Optical Proximity Correction (OPC), Phase Shift Mask (PSM), Source-Mask Co-Optimization (SMO), and so on, among others, each contributing significantly to achieving noteworthy outcomes. SMO, specifically, stands out by optimizing critical process parameters like Exposure Latitude (EL), Depth of Focus (DoF), and Mask Error Factor (MEF) for patterns governed by specific design rules. It accomplishes this by formulating a Cost Function, which, through SMO can significantly widens the process window for these patterns, ensuring compliance with manufacturing specifications. In this report, we studied the 7 nm node Back-End-Of-the-Line (BEOL) Metal layer’s process. Based on the definition of the design rules, the typical minimum pitch for this layer is 80 nm. We will select this minimum pitch for the patterns and combine it with other representative and characteristic patterns at this node to investigate the enhancement of SMO on the patterns at this technology node.

Efficient and accurate Proximity Effect Correction (PEC) is essential for Electron Beam Lithography (EBL) applications. Here we present an efficient PEC method by combining Cumulative Distribution Function (CDF) and separation of forward and back-scattering. Dose and shape hybrid corrections are used together to further enhance PEC accuracy. Compared to the traditional pixelation algorithms, the proposed method can enhance modeling efficiency by three orders of magnitude, while keeping the edge placement error (EPE) below one nanometer, in our testbench calculations. The proposed method might be useful in large-scale Mask Data Preparation (MDP) and direct-write EBL applications.

In the integrated circuits field, the rapid and accurate detection of defects and anomalies is a critical factor in improving lithography process yields. Research on large-scale chip layout pattern feature extraction and clustering algorithms plays a crucial role in enhancing chip manufacturing yield and improving manufacturing processes. This paper proposes a graph matching-based clustering method, leveraging the high redundancy and relatively simple circuit structure of chip layout patterns. Our method innovatively employs a graph-based representation to capture keypoint information in layout patterns, applies dual-similarity constraints to ensure both node and edge similarities, and utilizes agglomerative hierarchical clustering to merge structurally similar patterns, reducing the reliance on typical values. These enhancements allow for better handling of complex geometries, thus improving the efficiency and stability of pattern clustering. Compared to traditional clustering methods based on image statistical characteristics, our approach considers the geometric constraints within the chip layout, achieving effective clustering on large-scale chip layout patterns.

As the production scale of HVM expands, the daily generation of measurement images and defect images increases significantly. Identifying the root causes of such a vast number of failure images remains a challenge. Insufficiently determined failure reasons and subsequent blind process modifications can be detrimental to mass-produced products. This article discusses extensive sampling and measurement of wafer samples, utilizing contour extraction and subsequent data analysis to identify numerous failure patterns that do not meet product requirements. By clustering these failure patterns, we can obtain overall distributions of similar patterns in terms of CD, EPE, etc. By integrating statistical methods with actual wafer processes, we present quantitative solutions for correcting these patterns. Using an iteratively developed new product as a case study, we show that pre-launch layout analysis, alongside the extensive measurement analysis previously discussed, results in a CD distribution and average yield that surpass those of earlier generation products. This validates the feasibility and reliability of our approach.

As the number of 3D stacking layers continues to increase and the thermal design power of logic chips escalates, thermal management is confronted with unprecedented challenges. The temperature of the surface to be treated is also a parameter that is difficult to measure non-invasively. The standard technique is infrared (IR) pyrometry. However, due to the transparency of Si wafers in the IR spectrum, it cannot be used in the low-temperature regime (0°C ~ 400°C). In this study, a new low-temperature thermal measurement method was developed, utilizing Mueller Matrix Spectroscopic Ellipsometry (MMSE) combined with Thermo-Optical Coefficients (TOC). Firstly, the coefficients of the Cauchy dispersion equation for Si-based SiO₂ films were measured at different temperatures. The experimental results indicated that the refractive index of SiO₂ films exhibits high sensitivity to temperature in the ultraviolet to visible spectra. Subsequently, MMSE was combined with deep learning to reverse characterize the temperature in the chip overlay region. The results indicated that effective Mueller matrix elements and multi-channel deep learning could accurately identify the temperature in the overlay region, with an accuracy of 99.81% and a recognition precision of 1K. The proposed method contributes to optimizing automatic process control, alleviating wafer deformation and overlay errors caused by thermal management, thereby enhancing the reliability of high-bandwidth memory.

In semiconductor manufacturing, the detection of defects efficiently and accurately plays an important role in improving production quality and process optimization. However, most of the current defect inspection methods need to collect reference images on wafer. Based on the machine learning (ML) model, this paper first using the layout to generate the corresponding Scanning Electron Microscopy (SEM) image as the reference image for defect, and then by comparing the similarity of the defect image with the generated reference image to achieve accurate identification and localization of the defect. Experimental results demonstrate that the accuracy of this method for defect inspection is 98%, at the same time, the processing speed is at 100 image levels per minute. This study can not only improve the accuracy and efficiency of defect inspection, but also provide new ideas for the processing and multi-classification of defect images.

In a HVM, pinpointing process issues is crucial, as it directly affects product quality and production efficiency. Accurate fault localization helps teams quickly identify potential process defects, avoiding resource waste and time delays. However, troubleshooting process problems typically relies on indirect data analysis. Teams collect and monitor changes in various parameters, such as recipe parameters, environmental variations, and equipment differences, to infer possible root causes. This article proposes a direct troubleshooting method based on contour and statistical analysis. By directly comparing the graphical differences between different step processes and analyzing changes in Critical Dimension (CD) distribution, it is possible to pinpoint issues from overall process variations to specific changes caused by individual step processes. This approach shortens the troubleshooting steps and reduces the time needed to resolve problems. Additionally, because it goes beyond simple variation comparison and quantifies it using CD values, it allows for the disaggregation of localized variation amounts within the dimensions of SEM images. Therefore, this method not only reduces the number of inspection sites for troubleshooting but also provides insights into the degree of deterioration between each site, facilitating quicker problem resolution.

Transmission Electron Microscopy (TEM) uncertainty can stem from sample preparation, TEM measurement, and sample tilt during imaging, leading to result variations. Since TEM data serves as a reference for optical critical dimension (OCD) setup, reducing TEM uncertainty is essential to enhance OCD measurement accuracy. This work aims to address these challenges by optimizing sample preparation techniques, refining TEM measurement protocols, and minimizing sample tilt effects. By systematically identifying and mitigating sources of uncertainty, we aim to establish more reliable TEM data. The improved accuracy of TEM measurements will, in turn, enhance the precision of OCD setups, leading to more consistent and accurate process control in semiconductor manufacturing. This initiative not only aims to bolster TEM reliability but also to ensure the robustness of OCD measurements, thereby improving overall process quality and yield.

As the integration circuit manufacturing enters the advanced technology nodes, computational lithography encounters a big challenge in breaking through the limitation of lithography image fidelity. This work introduces an information theoretical method to explore the limit of image fidelity for advanced computational lithography. An information channel model is built up to depict the information transfer between the mask and print image, and the extension to include the characteristics of extreme ultraviolet lithography imaging model is discussed. Then, the methods to calculate of optimal information transfer for advanced computational lithography is briefly introduced, and the theoretical limit of image fidelity is derived. The proposed method could also be applied to improve the solutions of traditional computational lithography techniques.

Optical proximity correction (OPC) is an essential technique for enhancing photolithographic image quality. Its effectiveness and efficiency largely depend on accurate resist modeling. The resist exposure and development processes involve complex nonlinear physicochemical reactions, presenting significant challenges for fast and precise modeling required for OPC. In our work, a Wiener-Padé resist model is proposed. Through various experiments, we validate that the Wiener-Padé model delivers excellent performance in terms of accuracy, generality, and speed. The proposed resist modeling method offers significant potential for advancing photolithography modeling and OPC in contemporary semiconductor manufacturing.

Due to integrated circuit evolution to lower technology node, the complexity of lithographic process is steadily increasing. Therefore, lithography simulation technology has become more essential as a tool to guide the design of lithography materials, tools and processes for semiconductor industry. In this paper, we use lithography software to run simulation in order to understand the 3D topography of actual wafer, lithography and the effects of development parameters on critical dimension. The result shows the trend of simulation contour CD on layer-A/B/C fits well with the SEM trend. The simulated profiles are also evaluated and compared with SEM images.

Electron Beam Lithography (EBL) has advantages in high resolution imaging. However, its resolution was limited by the proximity effect due to electron backscattering in solid materials. Current methods for correction of proximity effects, such as dose and shape corrections, are effective in improving accuracy, but their time cost is not negligible. This paper presents a method that uses TransUNet, trained with the results of traditional dose correction methods, to create an end-to-end model. This method maintains accuracy, simplifies data processing to improve computational efficiency, and enhances ease of use.

In the photomask manufacturing industry, producing defect-free photomasks is a significant challenge. The processes of defect inspection, repair, and metrology are employed to ensure masks are defect-free. Within this process flow, the Aerial Image Measurement System (AIMS) metrology tool is widely used as the industry’s benchmark for evaluating defect printing impact and determining if a suspected defect requires repair. However, in the mature node photomask manufacturing, the product quantity is large, and the AIMS 248™ loading is heavy, sometimes doing AIMS review for all defects is expensive and time consuming. Thus, a fast, accurate, and economical method is desired which can simulate defect printability on wafer from images captured by photomask inspection tools, as a valuable complementary or backup method for AIMS to reduce the loading and increase the production efficiency. In this paper, we introduce Lithography Printability Review (LPR) to mature technology node mask manufacturing. It can simulate aerial images of defect with low cost, and short cycle time. On the Programmed Defect Mask (PDM), LPR demonstrated obviously improved efficiency without missing critical defects. For the production masks, LPR proved that it can save much time and improve production capacity effectively.

In the integrated circuit (IC) manufacturing process, defects directly impact the final product yield. Integrated circuit defects are characterized by a wide variety of defect types and complex circuit structures. We proposes a defect detection model based on multi-layer attention mechanisms, which enables the detection and classification of common defects in etching processes. First, we use a pre-trained backbone to extract features from different layers. Then, we perform feature encoding and fusion across these different layers. Finally, we utilize an end-to-end decoder to determine the location and type of defects. Compared to similar methods, our method shows a significant improvement in accuracy across different types of defects and requires fewer training samples. Some types of defects have already met the application requirements, and our approach incurs lower training costs when dealing with new types of defects, necessitating only fine-tuning of the model rather than retraining the entire network.

Precise patterns exposed by the most complicated machine called lithography in high-performance integrated circuits cannot be done without the capability of precise position. Due to the repetitive work demand, a method of FRF(frequency response function)-based modeling-free iterative learning control has been proposed for nano-scaled tracking of wafer stages with high dynamics and external disturbances. The proposed method is aimed at leaving out the modeling process to avoid modeling error and additional expenditure with no need for complex matrix calculation. In an attempt to deal with the adverse effects of iteration transient and random disturbances, an adaptive parameter is designed.

The rapid advancement of extreme ultraviolet lithography (EUVL) technology has significantly increased the difficulty of achieving defect-free mask manufacturing, thereby necessitating the development of high-sensitivity inspection tools capable of detecting minor defects on mask blanks. In response to this challenge, we developed an advanced optical inspection tool based on scattering dark-field imaging (MS-DFI) system, utilizing an EUV source generated through high-order harmonic generation (HHG). The photon flux of the produced high-order harmonics, centered around the wavelength of 13.5 nm, is approximately 5.9×1010 photons per second. Our experiments demonstrated its capability to detect and provide clear inspection signals from defects as small as 2 μm in diameter on the mask sample surface. However, further analysis of the experimental results reveals that the inspection efficiency diminishes sharply with decreasing defect size, proving to be insufficient for defects smaller than the hundred-nanometer scale. To address this limitation, we employed a finite-difference time-domain (FDTD) simulation method to further investigate the potential of the HHG source in defect inspection. This method can accurately model light propagation and scattering phenomena, allowing for an in-depth analysis of the defect inspection signals. The simulation results reveal a pattern consistent with Mie scattering theory. Additionally, we conduct a study of various orders of HHG sources with different wavelengths to evaluate their effectiveness. Our findings indicate that longer wavelengths, such as 38nm, exhibit a higher potential for detecting smaller surface defects, providing a promising direction for enhancing mask defect inspection systems.

In general, the NTD and PTD processes use a mix of anti-reflective and photoresist materials, which were influenced by two identified factors: Acid-base balance and surface tension matching. This paper focus on positive development process which involves washing away overexposed areas and leaving on unexposed areas. Therefore, to reflect good hydrophobicity and demonstrate superior adhesion in non-exposed regions, the anti-reflective substance must be linked to the photoresist. Acid-base unbalance can lead to a significant reduction in exposure and increase the chance of failure. If the acidity of the Anti-reflective material is excessive, it will make the bottom of the photoresist form undercut profile due to too much photo acid, which will lead to dense graphic collapse. In order to prevent the undercut profile effect, we determine the reason by using the failure mechanism, which uses alkaline substances to suitably neutralize the quantity of photo acid at the bottom. This eliminates the influence of the photo acid reaction at the bottom that contributes to the formation of a normal graph.

As the feature size in semiconductor manufacturing approaches 28nm and smaller, the impact of mask thickness in photolithography becomes increasingly significant, resulting in Edge Placement Errors (EPE), overlay issues and process window reduction, collectively referred to as 3D effects. The influence of the mask 3D effects come primarily from three factors: absorber topography coupling, mask structure-induced electromagnetic field variations, and lithography-induced shadowing. These effects challenge conventional mask correction strategies and pose a risk to maintaining high yield rates. A new, rule-based modeling approach is proposed to capture and correct 3D effects. The goal is twofold: to ensure that lithography imaging processes maintain high fidelity and to balance the accuracy and performance in full-chip simulations with a good model flexibility. The research presentation progresses through the introduction and priori works of the subject area, near field and other theoretical analysis, then the proposal about a new fast M3D correction method that brings benefits to mitigate a few challenges in existing simulation methods. Finally, an application test case on 28 node dimensions is provided and conclusions are made thereafter.

Existing infrared micro-thermal imaging often faces low resolution and contrast issue, which hinder its applications in high-precision integrated circuit inspection. Based on the advanced super-resolution techniques, high-resolution infrared images can be reconstructed from low-resolution measurements. Recently, diffusion models have shown strong capacity in the image reconstruction tasks. However, due to the low signal-to-noise ratio and inferior contrast, directly applying the traditional diffusion models to the infrared image is hardly to obtain high-quality super-resolution results. In this work, we first design a degradation model for real infrared imaging systems, and then we design an infrared super-resolution diffusion model based on ResShift, which introduces uncertainty into the u-net to enhance the robustness of the model and the reconstruction quality of the infrared images. The proposed method is validated based on a set of numerical experiments.

We have been developing an EUV microscope for actinic mask inspection based on a bending magnet beamline in Shanghai Synchrotron Radiation Facility (SSRF), China. The new microscope has a Fourier synthesis illuminator via scanning a Fresnel Zone Plate (FZP), and an off-axis FZP for imaging, which provides a theoretical spatial resolution of 33nm. In this work, we will present the optical and mechanical design of the microscope. We have validated the design and performance of the microscope by using a visible laser. We expect to have the microscope installed in SSRF and obtain preliminary results using 13.5nm EUV by the end of this year.

The latest generation of EUV lithography has launched in the market; the higher numeric aperture and more powerful light source bring additional challenges for vacuum and exhaust gas management providers. From an environmental view, EUV owners expect the vacuum subsystem to perform a better carbon footprint than the last generation of the EUV system. This paper will discuss dealing with a higher flow rate of clean hydrogen gas and reducing utility usage simultaneously. The field running result and future improvement plan will be shared. Furthermore, some hydrogen can be reused through an exhaust management system, thus reducing hydrogen consumption by up to 80%.

On Product Overlay (OPO) challenges are known to be the yield limiters in semiconductor manufacturing processes, as process control performance highly depends on the design and quality of the overlay (OVL) metrology targets. Innovative overlay target designs are needed for OPO reduction, overlay accuracy improvement and measurement robustness enhancement. The Metrology Target Designer (MTD) tool is widely used as an integral simulation method for overlay metrology target design, by co-optimizing lithography and metrology performance. Using this approach, one can simulate and analyze the overlay metrology target’s inherent performance and compatibility to inherent process variations. This paper presents how MTD can boost the Image-Based Overlay (IBO) measurability accuracy and robustness to common process variability issues. A customized MTD solution with Archer™ overlay metrology recipe optimization is developed and proven to address these manufacturing challenges.

The main hurdle in developing new IC technology nodes is the absence of high-quality, comprehensive layouts that can thoroughly test process capabilities, design and process interaction. In the initial stage of process development, it's necessary to define process specifications, specify OPC recipes, and establish design rules to confirm layout manufacturability. Each of these crucial tasks requires chip layouts to assess the quality, precision, and completeness of development outcomes. This paper primarily discusses how to utilize layout slicing to assemble a large layout. It involves cutting the hotspot-free design and contour layouts into slices of different sizes, enriching these slices through flipping, and then randomly assembling the enriched slices to form a large layout.

OPC technology is one of the most key procedures in IC manufacturing. When it came to the 90nm node process, lithography table-driven OPC technology was replaced gradually by the model-based OPC. In the early stage, optical model played a dominant role in whole OPC model, resist model provided limited adjustment on aerial images. As the technical node continue shrinking, and pattern complexity increasing, simplified resist model can’t perform resist behavior sufficiently. The properties of strong shrinkage and queue-time sensitivity posed a great challenge to resist modeling. Plenty of new resist model forms are introduced to describe the complex properties. Huge amounts of SEM measurement data are in need to serve model coverage for the complex pattern structures. Currently the gauge amount of measurement data could be over 10 thousands, OPC modeling becomes a big CPU and time consumer. In order to balance the run time and model accuracy, gauges are down sampled with random selection. Usually, around 5000 gauges are used for model calibration, and the left gauges are used for model verification. The weighted RMS values between calibration and verification should be in the same level, which represents the gauge selection could be considered as the reasonable replacement for the whole gauge data base. In this paper, we proposed a SONR (State Of Nature Reduction)- based gauge down sampling method. The SONR is a tool, which could classify the pattern structures and measurement values into specific clusters. With its help, the gauge amount for model calibration could be shrunk from 5000 to 3000. This method accelerated model calibration speed by nearly 1x time. In the meanwhile, it decreased CPU and license consume, and shorten R&D cycle of new OPC models.

The NA 0.33 EUV lithography tool is applied at 3nm logic node where the aberrations and 3D mask effects are difficult to eliminate. It limits resolution further reduced. In this paper, a Zernike polynomial-based pupil wavefront optimization (ZBPWO) technology for NA0.33 EUV is proposed. An active wavefront is applied to the imaging model which consist of 64 Zernike polynomials using an inverse optimization algorithm. The optimal pupil wavefront can improve image quality effectively. Simulation results show that the ZBPWO method reduce the pattern error about 50%. It demonstrate the impact of aberrations and 3D mask effects are controlled very well.

As semiconductor process technology advanced and integrated circuits design layout complexity escalated, process weak points detection plays an important role in the manufacture, which affects the final yield of the production. Design-Technology Co-Optimization (DTCO) is also proposed to reduce the cost and cycle time from design to market in advanced process development. Sub-Resolution Assist Feature (SRAF) is a common method adopted extensively in Optical Proximity Correction (OPC) to improve process window, the main challenge is balancing SRAF size, location, process window and printing issue. In this work, we take the advantages of OPC process simulation to proactively identify potential weak points and analyze which regions need to be modified to enlarge process margin, meanwhile provided guidelines to remove process un-friendly pattern or optimize design layout.

Directed self-assembly of block copolymer (BCP) has been extensively explored in application of contact hole multiplication at the sub-7 nm technology node. The aim of this study is to investigate the effect of surface affinity on the directed self-assembly of BCP, polystyrene-b-poly (methyl methacrylate) (PS-b-PMMA) for contact hole multiplication. The sidewall affinity of the guiding templates for PS and PMMA blocks is manipulated by controlling the grafting process or the PS mole fraction (fPS) of the brushes, which is favorable for tuning the Center-to-Center Distance (CCD) of the twin-hole pattern. The result demonstrates that the CCD increases with increasing the sidewall affinity for PS block of BCP, which is promising to fabricate high-density hole patterns at the sub-7 nm technology node.

As advanced process nodes demand increasingly tighter overlay error tolerances, overlay measurement has become more crucial, and the challenge to maintain high measurement accuracy has intensified. It is well known that IBO overlay measurement, which utilizes image-based measurement techniques, is significantly affected by image noise, impacting the final measurement accuracy. This issue becomes particularly evident when the substrate patterns are complex, as noise from different wavelengths becomes more pronounced. For different layers, the optimal measurement wavelength may vary, but actual measurements are limited to a single wavelength, resulting in an inability to eliminate much of the image noise, which in turn affects measurement accuracy. This paper proposes improvement solutions focused on reducing the impact of image noise, from measurement tools to model processing, in order to enhance the accuracy of IBO measurements.

Directed Self-Assembly (DSA) of cylindrical block copolymer with graphoepitaxy strategy offering significant potential for contact hole multiplication in semiconductor manufacturing at technology nodes below 7 nm (sub-7 nm). This technique allows precise control over the number of DSA-generated holes and their critical dimensions (CD) by manipulating the guiding template geometry and size. The results indicate that DSA quadruple-hole multiplication patterns aligned top-bottom and left-right, with a long-axis spacing of 55-65 nm and a short-axis spacing of 30-40 nm could be achieved through precisely designing template holes with long-axis dimension and short-axis dimension. The formed DSA pattern was successfully transferred to the underlying hard mask layer, creating a large-area quadruple-hole array with a CD of approximately 17 nm. A comprehensive investigation of guiding template size and morphology on multiplication hole patterning enhances the understanding of the self-assembly behavior in confined elliptical spaces. In conclusion, this work highlights the importance of optimizing guiding template size for contact hole multiplication in integrated circuit fabrication.

Extreme Ultraviolet Lithography (EUV) and other advanced manufacturing technologies have increased the demand for characterizing 3D integrated structures. Due to the inability to directly access and observe buried interfaces, existing metrology tools face significant challenges in this area. Sum Frequency Generation (SFG) spectroscopy, with its surface and interface selectivity, non-destructive nature, and high sensitivity, represents a feasible option for probing molecular interactions at these buried interfaces. However, the nonlinear characteristics of SFG spectra and the coupling between spectral components make manual spectral decomposition highly complex, requiring extensive experience in spectral analysis and is relatively time-consuming, while the stability can hardly be ensured. This severely limits the application of SFG in large-scale, high-throughput characterizations. To overcome this bottleneck, we have developed a toolkit for the decomposition process by integrating advanced deep learning techniques, specifically a Multi-Layer Perceptron (MLP) network with custom activation functions. This toolkit reduces the analysis time from several hours to just a few minutes, while maintaining high accuracy compared to manual operations.